Figure 1: MOS 6502.
The key component of the NES system is the MOS 6502 CPU. This is the main processor where the game's code is executed. This CPU was very popular in the 1980's where it was used in some of the first personal computers including the Commodore 64, Apple II, and the Atari systems. As a result, there is plenty of documentation on writing code for the CPU which includes the instruction set, instruction cycle times, and IO information.
The 6502 is a 8bit Data - 16bit Address CPU, accumulator based processor with multiple instruction lengths. There are three interrupt methods, maskable and non-maskable, and a reset interrupt, which are all used by the Nintendo system. There are 5 program visible registers usable by the code. There is an 8bit Accumulator which performs all of the math operations, two 8bit addressing registers X and Y, an 8 bit Stack register for subroutines and interrupt handlers, and a 16 bit Program Counter.
The instruction set is fairly simple, only 52 different types, which are mostly numerical operations with support for subroutines, stack operations, and branching. There are however 13 different addressing modes for which instructions can get their operands. These include direct addressing, indirect addressing, zero page, indexed, index indirect, and indirect indexed (the addition of the indexing register is done after the indirect fetch). These different addressing modes and the presence of two different addressing registers X and Y add a lot of complexity to the instruction set. Furthermore, instructions can all be of different length. For example, a one byte instruction would be TAX (Transfer Accumulator to X register) that does not require any other arguments. However LDA $2006 (Load Accumulator with value at address $2006) requires three bytes, AD (the op code for LDA absolute address), 06, 20 (the address). These different addressing modes expands the number of opcodes up to 149 from the original 52 instructions. Furthermore the timing specifications for how many cycles these instructions take to complete are also specified and are different per instruction. The implementation of the CPU must conform to these expectations for it to be a 100% compatible CPU. Furthermore, the code written for the Nintendo expects these timings to be accurate since it was written only to perform on this Cpu.
The literature available regarding the 6502 only defines the behavior of the CPU from a programmer's perspective not at a hardware level. It is clear that there are internal registers that are used for buffering data for each of the cycles of the instructions that will need to be designed. This kind of specification is perfect for this project since it is the hardware level that is to be designed.