- Summary Paper
- This summary paper briefly describes the two projects I worked on and presents
some of my thoughts on software development.
Paper
- SimPLC
- Ladder Logic PLC (Programmable Logic Circuit) Simulator. This software was
developed on behalf of Dr. Jeff Jackson
of the UA Department of Electrical Engineering.
Screen Captures
User Documentation
.zip format archive of all source and documentation (439K)
- PAV
- The Parallel Algorithm Visualizer was developed on behalf of
Dr. Richard Borie of the UA Department of
Computer Science. It was created as a tool for converting lecture notes and
transparencies illustrating the execution of some simple parallel algorithms
into animated simulations.
Screen Captures
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