A Hardware F-Buffer Implementation

 

Mike Houston

Stanford University

Arcot Preetham

ATI Technologies Inc.

Mark Segal

ATI Technologies Inc.

 

Stanford Technical Report

 

Abstract

 

This paper describes the hardware F-Buffer implementation featured in the latest ATI graphics processors. We discuss the implementation choices made in each chip and the various implementation challenges faced like overflow handling. The F-Buffer was originally intended as a solution for multi-pass shading. We demonstrate this functionality, comparing it to traditional multi-pass rendering techniques, and show performance results. Given hardware F-Buffer support, we describe extended uses like order independent blending. We also show how a future F-Buffer implementation might be extended to allow more advanced operations like data filtering.

 

 

 

Paper

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