Visualizing Application Behavior on Superscalar Processors
Pat Hanrahan, and
Computer Science Department
Appears in Information Visualization '99
The advent of superscalar processors with out-of-order execution makes
it increasingly difficult to determine how well an application is
utilizing the processor and how to adapt the application to improve
its performance. In this paper, we describe a visualization system
for the analysis of application behavior on superscalar processors.
Our system provides an overview-plus-detail display of the
application’s execution. A timeline view of pipeline performance data
shows the overall utilization of the pipeline, indicating regions of
poor instruction throughput. This information is displayed using
multiple time scales, enabling the user to drill down from a
high-level application overview to a focus region of hundreds of
cycles. This region of interest is displayed in detail using an
animated cycle-by-cycle view of the execution. This view shows how
instructions are reordered and executed and how functional units are
being utilized. Additional context views correlate instructions in
this detailed view with the relevant source code for the
application. This allows the user to discover the root cause of the
poor pipeline utilization and make changes to the application to
improve its performance.
This visualization system can be easily configured to display a
variety of processor models and configurations. We demonstrate it for
both the MXS and MMIX processor models.
PDF (6.8 MB),
PostScript with lo-res figures (1.9 MB) or
PostScript with hi-res figures
(1.9 MB gzipped, 18 MB uncompressed).
Last modified: Mon Jan 24 17:16:03 PST 2000