With a complete datapath and control logic implemented the testing of the CPU can begin. This stage is where the design tools using in the implementation make significant impact on design process. It is critical in creating a fully functional CPU, that any bugs that exist within the design can be detected quickly and provide a clear location of exactly where the design failed.
In the 6502 design, the VHDL modules were tested with a commercial package, called Synopsys, that provides signal and state information at any level of the hierarchy of the design. Explained in sections above, the modular design of the datapath provides a much cleaner description of what is happening with in the CPU at any point.
Figure 6: The Sysnopsys signal tracer.
To test the design, a testing environment was created where the CPU is connected to a primitive memory device which loads its contents from a file. This file contains that test program that can be used to test the different states within the control logic. The debugging environment simulates the hardware and provides signal outputs which provide the necessary debugging info.