The control logic for 6502 was designed to contain the minimal number of states to try to simplify the actual gate logic once it is compiled. Also it is crucial as mentioned previously, to match the actual 6502 cycle times.
Each instruction begins with the same two fetch states. The first fetches the instruction using the program counter, the next fetches the first operand while decoding the instruction. The one cycle ops need to be performed during the second fetch, otherwise more cycles are needed.
Decoding the 149 different op codes efficiently is no simple task. This required studying the different op codes to understand why the original engineers of the 6502 chose the different encodings. In general the addressing information, which addressing mode to use, is somewhat consistent across the different op codes.
Next there are different states for each of the different addressing modes. For example, Indexed Addressing requires an extra state for adding the index register to the base passed through the first operand, while in immediate instructions the operand that was fetched in the second cycle is the value to perform the operation on. The remaining states handle the actual execution of the instruction after the operand has been successfully fetched.
Finally there are specific states for the Program flow commands which include jumps, subroutines, and interrupts.