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Instruction Grouping

Since it is impractical to go through each of the 52 instructions and define each step, we can group instructions that perform similar operations. The simplest grouping are one cycle ops. These instructions like, TAY (Transfer Accumulator to Y register) or TXS (Transfer X register to Stack register), define basic connectivity within the datapath. There must be a direct connection between the Accumulator and the input of the Y register. Since this operation must be done in on clock cycle, there cannot be an intermediate clocked flip-flop, since that would require two clock cycles.

The next grouping is the read instructions. These instructions only require the reading of an operand and writing to a particular register with an operation. These instructions include ops like, LDA (Load Accumulator) or AND (And Accumulator with Memory). These instructions do not modify memory, only registers. They must take more than one cycle to perform since they require an operand to fetch.

Opposite to the read group, are the read-modify-write group. These instructions do modify memory contents with instructions like, ROL (Roll Left) or DEC (Decrement Memory). These require extra cycles and must have buffer registers since the alu must perform the operation then be able to write it back.

Also both the read and the read-modify-write group have different addressing modes in which they can fetch their operands. Although they perform the same operation once they get the value they are to perform on, they may take extra cycles to fetch the value they need. Therefore, each of the different addressing modes must be worked out to determine what type of datapath connections and buffer registers are needed.

Read Instructions

tabular46

Write Instructions

tabular52

Read-Modify-Write Instructions

tabular58

Addressing Modes

tabular64

Finally, control flow instructions must also be considered since they will typically define what datapath connectivity is required between the program counter and the rest of the datapath.


next up previous
Next: Register Transfer Design Up: Instruction Timings and Datapath Previous: Instruction Timings and Datapath

Ian A. Buck
Wed May 20 12:50:42 EDT 1998