Lightning

Lightning is our first distributed framebuffer architecture for Flash Graphics. Previous software parallel graphics systems have suffered from the lack of low-latency, high-bandwidth displays. Lightning directly addresses this problem by providing a distributed framebuffer accessible in parallel to maximize draw bandwidth, paired with a unified memory architecture for minimum latency.

This research addresses a number of current problems:

Low Latency and High Bandwidth: Memory refresh is performed from system memory, for latency comparable to contemporary high-end graphics computers. Our target systems have memory system bandwidths of several hundred megabytes per second, and large caches, providing more than an order of magnitude more bandwidth than vanilla PCI.
Partitionability: The Lightning ports may be software partitioned into groups, allowing the use of multiple independent displays simultaneously. Lightning follows in the trend of current multiprocessor systems, allowing all of the Lightning boards in a system to be partitioned. The boards may be allocated as coarsely as all to a single very demanding user to a single board per user, with commensurate performance tradeoffs.
Virtual Window System: The use of system memory for the frame store allows a powerful virtual window abstraction to be implemented, while avoiding the difficulties of traditional window systems based on a single framebuffer.

Each Lightning framebuffer port consists of a RAMDAC, a modest amount of datapath hardware to transport pixels between ports, and a PCI Pamette, a reconfigurable logic board from Digital. The reconfigurable logic provides both ease of design, adaptability to future interface changes, and a flexible platform for experimentation.
A board set is shown at right. The board in the back is the Pamette, which is connected by a ribbon cable to the Pamette. The white ribbon cable coiled on the left hand side is the PixelBus interconnect, which cables the Lightning boards together. Each Lightning board has both a PixelBus input and output cable.

A Lightning board is shown in detail above. At the far left are the BNC connector for video out. The square chip to their immediate right is the RAMDAC. The 3 columns of chips close to the center of the board are registers and multiplexers for routing data on the PixelBus. The 3 large square chips are the pixel FIFO. The round silver package at the far right is a voltage regulator.

Lightning decomposes the responsibility for display in screen space, programmably assigning pixels for display to individual Lightning boards on a 4-pixel basis. Typical tiling schemes will be more regular, as shown on the right. Here 3 boards are acting in concert to refresh a single display. The pixels on the display are retrieved via a scatter/gather table, allowing flexible memory arrangements.

Our choice of a PCI interface has made our hardware readily portable. Lightning is currently being targeted to both the Flash Multiprocessor and a network of Intel Multiprocessors.

In the future we would like to extend our hardware support to include rasterization support. This would allow us to utilize the immense floating point ability of contemporary processors in conjunction with massive pixel computation ability of custom hardware. A tentative architecture is shown at right. Here the microprocessor at a node in the Flash machine has been replaced by a small array of Graphics Engines (GEs).

Lightning is being developed by Matthew Eldridge, John Owens and Kekoa Proudfoot with Professors Pat Hanrahan, Anoop Gupta and Kai Li.

Intel Corporation has provided valuable advice and financial support of Lightning.

eldridge@graphics.stanford.edu