Since we are using the provided datapath and memory structure, the block diagram primarily shows the workings of the controller FPGA. The combinational logic which manages the display latch is shown. The Code latch maintains which code the user selected when the display button was pressed. This value is stored as a 3 bit latch and is decoded into an 8 bit one-hot and compared with each of the load signals for the registers. The comparator's output is high when the code matches the proper load signal and the value is grabbed off the bus. Extra signal are defined for registers or other inputs that are not directly loaded of the bus (ShowEA, ShowIR, ShowSR). These signals are asserted manually in the ASM so they too can be latched. Furthermore, the LoadLed signal is also available to force the Display latch to grab the value on the bus.