For the control and datapath, we used two separate chips instead of one. The controller was a Xilinx 4010 while the datapath Xilinx 4003 using the team Zorro's datapath design.
We used two separate chips because we didn't see much advantage to placing everything onto a single 4010. Although wiring would have been simpler, the two chip design offers easier debugging with the logic analyzer, simpler VHDL coding, and less constraints on VHDL design. Also by separating the datapath and control, we were able to onboard test each component before connecting them together.