Next:
Introduction
Up:
PD-PP Final Report
Previous:
PD-PP Final Report
Contents
Introduction
Design Organization and Summary
Front Panel and Display Leds
Control and Datapath Design
Block Diagram
Control Fundamentals
ASM Chart
The IDLE state
The DSPLY state
The EXEC state
The F1 state
The E1 state
The E.OP state
The E.IOT state
PC Parallel Port
The PC parallel port
Inputting into the PD-PP
Outputting out of the PD-PP
VHDL Code
Timing Glitches
Testing the design
Final Results
About this document ...
Ian A. Buck
Mon Apr 20 20:49:25 EDT 1998