next up previous contents
Next: Timing Glitches Up: PD-PP Final Report Previous: Outputting out of the

VHDL Code

The VHDL went through numerous revisions until a complete controller was implemented. The implemention was done in stages, first implementing the IDLE, EXEC and DSPY stages to get basic loading and displaying to work. This was downloaded to the controller chip and tested.





Ian A. Buck
Mon Apr 20 20:49:25 EDT 1998