Once that version of the VHDL was working, we implemented the next version in accordance to the labs assigned. We found that as the size of our design increased, the timing characteristics worsened. A lot of time was spent flattening the VHDL into more states and less if's to simplify the design.
The problems were occurring within state changes. Since in the unoptimized VHDL the logic was so cascaded, certain signals coming out of the controller would glitch or not change in sync with the datapath.
To solve most of these problems, all control signals were ANDed with the NOT Clock. This made sure that the state was stable before any of the signals changed. Furthermore, the ASM was flattened to include more states and less conditional statements. In fact, to get the PD-PP to operate at 3 Mhz, the microcode ASM was drawn out into four states which gets processed for every micro opcode.